In a CMOS device, ESD protection is very important if the source and drain regions of the outer transistors of the integrated circuit (IC) are silicided. As a result, these source and drain regions have very low resistivity. In the areas of the respective source and drain regions adjoining the field-oxide regions and the gate regions, including the spacers, very high field strengths can be produced. Through charge carrier multiplications, current paths may then be provided in these regions, which, because of the low series resistance of silicided leads, can result in the device being destroyed. The input and output transistors are particularly affected, because high charging voltages of approximately 1000 V are frequently developed there. To avoid such current paths, a special SALICIDE process is carried out. In this process, those areas of the source and drain regions of the respective outer transistors (output, input, protective transistors) which adjoin the field oxide regions and the spacers of the gate regions are protected from the siliciding by a protective oxide layer. This layer is relatively thin and is deposited by a chemical vapor deposition (CVD) process. The layer is suitably patterned using an ESD mask to form a masked or masking protective oxide layer. The masking protective oxide layer is commonly formed by a photoresist process and a subsequent etching process. The subcircuits of the integrated circuit (IC) which are not connected directly to the outside world, which is generally the case for the greater part of the IC, need not be directly protected. From these, therefore, the protective oxide layer is completely removed in the etching step. Details of the other steps involved in fabricating the CMOS device which are not described here are familiar to those skilled in the art.
A CMOS device with ESD protection has been described in U.S. Pat. No. 5,262,344 entitled "N-CHANNEL CLAMP FOR ESD PROTECTION IN SELF-ALLIGNED SILICIDED CMOS PROCESS" which was issued to K. R. Mistry and assigned to the Digital Equipment Corporation. The ESD protection device in this patent is formed in an integrated circuit by a N-channel grounded-gate transistor. The siliciding of the protection device is controlled so that the adverse effects of ESD events are minimized. There are no silicided areas created on top of the polysilicon gate of the protection transistor, nor on the source/drain regions near the gate and self-aligned with the gate, in contrast to the siliciding of other transistors made by the CMOS process.
In the process of forming a CMOS device, a problem arises involving the masking protective oxide layer which is deposited on other oxides, such as the field and spacer oxides. This masking protective oxide layer is removed from the field and spacer oxides, particularly in the inner portion of the IC, by etching. The problem arises in that the field and spacer oxides may be damaged by these etching processes. It is very important, however, that field and oxide spacers remain undamaged in the process, because otherwise the configuration and circuit parameters of the IC will change. The '344 patent, discussed above, does not address the problem of etching processes on the field and spacer oxides which may be damaged by these processes.
It is therefore an object of the present invention to improve the process of fabricating a CMOS structure in such a way that the circuit parameters of the device are not changed, and reliable ESD protection is ensured.